Hardware Forge

Crafting the revolution of semiconductors

a research group from the Politecnico di Milano

Theses

We currently offer thesis projects in processor architecture, computer security, machine learning, and on-chip interconnects. If interested, write us an email.

Adaptive Instruction Prefetching for Modern SoC Workloads

Study instruction prefetching methods that adapt to different workloads and evaluate their effects on modern system-on-chip performance.

Development of Side-Channel Attacks on Commercial TPUs: Physical and Microarchitectural Threat Landscapes in Edge AI

Investigate physical and microarchitectural side-channel risks in commercial tensor processing units used for edge AI.

Analysis of the Impact of Microarchitectural and Architectural Features of Modern Processors on the Susceptibility to Transient Execution Attacks

Analyze how processor architecture and microarchitecture affect susceptibility to transient execution attacks.

Development of Machine Learning Methodologies for Security Attacks Detection and Prevention Based on On-Chip Measurements

Develop and assess machine learning methods that use on-chip measurements to detect and help prevent security attacks.

Development of Transient Execution Attacks against NIST Post-Quantum Cryptography

Study transient execution attacks against implementations of post-quantum cryptography standards selected by NIST.

Multicast-Capable NoC Routers for Coherence Traffic in RISC-V Multicore Clusters: Deadlock-Safe Routing and Protocol Co-Design

Design and evaluate multicast-capable network-on-chip routers for coherence traffic, with deadlock-safe routing and coordinated protocol design.

Topology-Aware NUCA over NoC for RISC-V SoCs: Placement, Migration, and Coherence-Driven Data Movement

Explore topology-aware data placement and migration in a non-uniform cache architecture connected over a network-on-chip for RISC-V systems.

Ultra-Compact NoC for RISC-V MCU-Class Multicores with Lightweight Coherence and Low-Power Links

Explore a compact network-on-chip for microcontroller-class RISC-V multicores, including lightweight cache coherence and low-power links.

Development of Novel Trusted Execution Environments (TEEs) (in collaboration with the European Space Agency)

Explore the design and development of trusted execution environments for protecting sensitive operations and data.

Design of Integrated GPU Architectures for RISC-V System-on-Chip (SoC) Platforms (in collaboration with the European Space Agency)

Explore GPU architectures integrated with RISC-V system-on-chip platforms.

Exploiting GPU Microarchitectures for Novel Hardware Attacks: Investigating Memory Leaks and Arbitrary Code Execution Without Physical Access (in collaboration with the European Space Agency)

Investigate GPU microarchitectural attack surfaces related to memory leaks and code execution without physical access.

Exploring Security Vulnerabilities in the OpenTitan Framework: A Comprehensive Analysis and Testing Approach (in collaboration with the European Space Agency)

Analyze the OpenTitan framework and test its components to identify and assess potential security vulnerabilities.