An experimental comparison of RISC-V processors: performance, power, area and security - Special Session Paper
E Lazzeri, BE Forlin, G Furano, M Ottavi, L Cassano
2024 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)
Paper

Lightweight Instrumentation for Accurate Performance Monitoring in RTOSes
Bruno Forlin, Kuan-Hsun Chen, Nikolaos Alachiotis, Luca Cassano, Marco Ottavi
2024 Design, Automation & Test in Europe Conference & Exhibition (DATE)
Paper

Built-in Software Obfuscation for Protecting Microprocessors against Hardware Trojan Horses
Alessandro Palumbo, Marco Ottavi, Luca Cassano
2023 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)
Paper

Improving the Detection of Hardware Trojan Horses in Microprocessors via Hamming Codes
Alessandro Palumbo, Luca Cassano, Pedro Reviriego, Marco Ottavi
2023 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)
Paper

Towards dependable RISC-V cores for edge computing devices
Pegdwende Romaric Nikiema, Alessandro Palumbo, Allan Aasma, Luca Cassano, Angeliki Kritikakou, Ari Kulmala, Jari Lukkarila, Marco Ottavi, Rafail Psiakis, Marcello Traiola
2023 IEEE 29th International Symposium on On-Line Testing and Robust System Design (IOLTS)
Paper

Is risc-v ready for space? a security perspective
Luca Cassano, Stefano Di Mascio, Alessandro Palumbo, Alessandra Menicucci, Gianluca Furano, Giuseppe Bianchi, Marco Ottavi
2022 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)
Paper

Processor security: Detecting microarchitectural attacks via count-min sketches
K Arıkan, A Palumbo, L Cassano, P Reviriego, S Pontarelli, G Bianchi, O Ergin, M Ottavi
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2022
Paper

DETON: DEfeating hardware Trojan horses in microprocessors through software ObfuscatioN
Luca Cassano, Mattia Iamundo, Tomas Antonio Lopez, Alessandro Nazzari, Giorgio Di Natale
Journal of Systems Architecture
Paper

Is your FPGA bitstream Hardware Trojan-free? Machine learning can provide an answer
Alessandro Palumbo, Luca Cassano, Bruno Luzzi, José Alberto Hernández, Pedro Reviriego, Giuseppe Bianchi, Marco Ottavi
Journal of Systems Architecture
Paper

On the optimization of software obfuscation against hardware trojans in microprocessors
Luca Cassano, Elia Lazzeri, Nikita Litovchenko, Giorgio Di Natale
2022 25th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)
Paper

Securing RSA hardware accelerators through residue checking
Ana Lasheras, Ramon Canal, Eva Rodríguez and Luca Cassano
Microelectronics Reliability, 2021
Paper

A lightweight security checking module to protect microprocessors against hardware trojan horses
Alessandro Palumbo, Luca Cassano, Pedro Reviriego, Giuseppe Bianchi and Marco Ottavi
2021 34th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems
Paper

Lightweight protection of cryptographic hardware accelerators against differential fault analysis
Ana Lasheras, Ramon Canal, Eva Rodríguez and Luca Cassano
2020 26th IEEE International Symposium on On-Line Testing and Robust System Design
Paper

A Microprocessor Protection Architecture against Hardware Trojans in Memories
Alperen Bolat, Luca Cassano, Pedro Reviriego, Oguz Ergin, Marco Ottavi
2020 IEEE International Conference on Design & Technology of Integrated Systems in Nanoscale Era
Paper

Protecting RSA Hardware Accelerators against Differential Fault Analysis through Residue Checking
Ana Lasheras, Ramon Canal, Eva Rodríguez and Luca Cassano
2019 32th IEEE Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems
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